Typical DRAMs (dynamic random access memories) have active cycles which include access cycles for accessing the memory cells and restore cycles for restoring data read from the memory cells. Following the active cycles, typically precharge cycles occur to precharge the bit and word lines of the memory array for the next active cycle. Row decoders generally provide the circuitry to precharge the word lines and to drive the word line voltages to access and restore addressed memory cells.
A typical memory cell configuration is shown in FIG. 1. A bit line 10 is coupled to a drain electrode of a transistor 12, illustratively an n-channel, enhancement mode field effect transistor. A gate electrode of transistor 12 is coupled to or formed by part of a word line 14. A source electrode of transistor 12 is coupled to one terminal of a capacitor 16. Another terminal of capacitor 16 is coupled to a constant voltage, VCP. Bit line 10 is typically coupled to a sense amplifier circuit (not shown). Word line 14 is typically coupled to a row decoder (not shown). Generally, an array of such cells is provided.
Capacitor 16 typically is charged to VCC to store a logical "one" and 0V for a logical "zero." To read from capacitor 16, bit line 10 is typically precharged to 1/2 VCC and word line 14 must be driven to a voltage greater than a threshold voltage above either the voltage stored in capacitor 16 or the precharge voltage of bit line 10, whichever is lower. VCP is typically 1/2 VCC.
Considering a DRAM having a 5 V power supply VCC, for example, if a "zero" (0 V) is stored in capacitor 16, word line 14 must be driven to at least one threshold voltage (.apprxeq.1 V) to turn transistor 12 on. If a "one" is stored in capacitor 16 (5 V), then the word line 14 must be driven to at least one threshold voltage greater than the precharge voltage of bit line 10. If bit line 10 is precharged to 2.5 V (1/2 VCC), then the word line should typically be charged to at least approximately 3.5 V.
After the memory cell is accessed and read, the data will be restored. In this case, word line 14 will be driven to a voltage that is at least one threshold voltage greater than VCC (5 V) to allow a full VCC (5 V) to be stored in capacitor 16 from bit line 10. Providing a voltage that is greater than the chip power supply is commonly done by the "bootstrapping" technique, well-known to the art.
Typically, when a 5 V DRAM is in an active cycle, word line 14 is driven as quickly as possible to VCC (5 V) for reading the memory cell. After the memory cell is read, the word line 14 is bootstrapped to a threshold voltage greater than VCC (5 V) for the restore cycle. Since the bootstrapping of word line 14 is not done during the critical access time of the memory cell, the timing of the bootstrapping is not critical. The timing that determines when word line 14 is driven from VCC to a voltage above VCC of the 5 V DRAM is typically generated by a conventional timer circuit that is not part of the row decoder configuration.
Progress has brought about decreased device sizes and geometries, and increased chip density. Typically, the smaller device size will not operate with a chip power supply of 5 V because it would damage the device. Therefore, these smaller devices use a lower power supply voltage, such as 3 V.
A memory cell like that shown in FIG. 1 for a 3 V DRAM would have bit line 10 precharged to 1.5 V (1/2 VCC). The voltage on capacitor 16 for a logic "one" will be 3 V (VCC). To read the logic "one" from capacitor 16, word line 14 must be driven to a voltage that is a threshold voltage greater than the precharged bit line voltage. To insure reliable reading of the memory cell, the word line voltage should be driven to approximately a full VCC (3 V).
An access time problem arises from these smaller device sizes of a 3 V DRAM that the 5 V DRAM may not have. The resistor-capacitor ("RC") characteristic of word line 14 causes a delay in word line 14 being driven to 3 V to read the memory cells. This delay may be seven or eight nanoseconds, and this is critical to access times. To overcome this delay problem, word line 14 is bootstrapped to a voltage greater than VCC, which shall be referred to as VCCP, to read the memory. One way to bootstrap word line 14 to VCCP is to use p- and n-channel transistors coupled to word line 14. VCCP may be provided by an on-chip charge pump. The p-channel transistor would have its source electrode coupled to VCCP, the drain electrode coupled to the word line 14, and the gate electrode coupled responsively to some internal signal within the row decoder (not shown). The n-channel transistor would have its drain coupled to word line 14, its source coupled to ground, and its gate coupled to some signal generated by the row decoder (not shown).
The p-channel transistor operates as a pull-up device that is turned on to pull word line 14 all the way to VCCP to read the memory cell. The transistor is then turned off after the memory cell data is read. The n-channel transistor operates as a pull-down device that is turned on to pull the word line to ground for the restore cycle. The problem with this approach is the p-channel transistor has less current drive capability than an n-channel transistor (of the same size) by approximately a factor of two. A very large p-channel transistor would have to be used to quickly drive the capacitance of word line 14.
An additional drawback to this approach is the p-channel transistor has to be laid out in a row pitch of a dynamic RAM which has very limited area. It is very difficult to lay out these p-channel transistors in the pitch and have them large enough to pull up word line 14 quickly. These transistors would consume a good deal of chip area.
FIG. 2 shows one prior art implementation of another bootstrap concept consisting of a generator 17, a predecoder 18 and a decoder 19. Generator 17 has a main input clock signal .phi.XG. Generator 17 also has various other inputs, and it outputs a master clock signal .phi.X+. Master clock signal .phi.X+ is boosted to VCCP to boost eventually a word line signal WL (an output from decoder 19) to VCCP. The various other inputs are used, for example, to reset master clock signal .phi.X+ low, precharge generator 17, boost a node in generator 17 to VCCP and precharge generator 17 at the start of row address strobe ("RAS") high precharge periods.
Predecoder 18 receives, among other signals, a clock signal .phi.XDP to precharge circuitry in predecoder 18 to a high state, master clock signal .phi.X+ and address bits which are used to enable the output of a predecoded boosted clock signal .phi.X+.sub.i. The variable i represents, for example, an integer between 1 and 8. Predecoded boosted clock signal .phi.X+.sub.i is boosted to VCCP, and is eventually supplied to a word line signal WL that corresponds to the variable.
Decoder 19 receives predecoded boosted clock signal .phi.X+.sub.i clock signal .phi.XDP to precharge circuitry in decoder 19 to a high state, and address bits to enable the output of word line signal WL. Word line signal WL is raised to VCCP when main input clock signal .phi.XG is active.
The drawback of the FIG. 2 implementation is that the wordline signal WL rises to VCCP after input signal .phi.XG becomes active. In an implementation such as FIG. 2, the wordline signal WL may be quite tardy in rising to VCCP. This brings about an unnecessary delay in restoring, refreshing and/or accessing the memory cells.
Another way to bootstrap a word line of a memory array to VCCP is to use a bootstrap decoder with either internal or external timing circuitry. The timing circuitry is designed with predetermined delays. The predetermined delays are usually determined from empirical data for the bootstrapping decoders. The timing circuit is usually implemented using inverters or RC time constant delay circuits.
This later approach has many drawbacks. The timing is not accurate for each decoder circuit i.e. the decoder circuit may or may not be ready to output a word line signal WL having a voltage VCCP when it is selected. In fact, the timing is usually delayed longer than need be for the sake of reliability. Also, the timing circuit does not provide compensation for temperature variations of the devices.
Therefore, it is the general object of the present invention to overcome the above-described problems.
Another object of the present invention is to provide a simple design to implement self-timing of the decoder circuit.